Parallel Computer Architecture Hardware Software Approach By David E Culler

About This Book... This book outlines a set of issues that are critical to all of parallel architecture--communication latency, communication bandwidth, and coordination of cooperative work (across modern designs). It describes the set of techniques available in hardware and in software to address each issues and explore how the various techniques interact. Table Of Content... Foreword Preface 1 Introduction 1.1 Why Parallel Architecture 1.1.1 Application Trends 1.1.2 Technology Trends 1.1.3 Architectural Trends 1.1.4 Supercomputers 1.1.5 Summary 1.2 Convergence of Parallel Architectures 1.2.1 Communication Architecture 1.2.2 Shared Address Space 1.2.3 Message Passing 1.2.4 Convergence 1.2.5 Data Parallel Processing 1.2.6 Other Parallel Architectures 1.2.7 A Generic Parallel Architecture 1.3 Fundamental Design Issues 1.3.1 Communication Abstraction 1.3.2 Programming Model Requirements 1.3.3 Communication and Replication 1.3.4 Performance 1.3.5 Summary 1.4 Concluding Remarks 1.5 Historical References 1.6 Exercises 2 Parallel Programs 2.1 Parallel Application Case Studies 2.1.1 Simulating Ocean Currents 2.1.2 Simulating the Evolution of Galaxies 2.1.3 Visualizing Complex Scenes Using Ray Tracing 2.1.4 Mining Data for Associations 2.2 The Parallelization process 2.2.1 Steps in the Process 2.2.2 Parallelizing Computation versus Data 2.2.3 Goals of the Parallelization process 2.3 parallelization of an Example Program 2.3.1 The Equation Solver kernel 2.3.2 Decomposition 2.3.3 Assignment 2.3.4 Orchestration under the Data Parallel Model 2.3.5 Orchestration under the Shared Address Space Model 2.3.6 Orchestration under the Message-Passing Model 2.4 Concluding Remarks 2.5 Exercises 3 Programming for Performance 3.1 Partitioning for Performance 3.1.1 Load Balance and Synchronization Wait Time 3.1.2 Reducing Inherent Communication 3.1.3 Reducing the Extra Work 3.1.4 Summary 3.2 Data Access and Communication in a Multimemory System 3.2.1 A Multiprocessor as an Extended Memor